This invention relates to integrated circuits, and more particularly to input-protection and electro-static-discharges (ESD) protection circuits.
Higher-density integrated circuits (IC""s) are made possible by advances in semiconductor manufacturing, especially by reducing transistor size. However, smaller transistors are more sensitive to damage from external shocks, such as electro-static-discharges (ESD). Thinner gate oxides can be shorted, and substrate junctions melted by relatively small currents applied to the tiny devices. Static charges from a person or machinery can produce such damaging currents.
The input/output (I/O) pads of a semiconductor chip almost always have special protection circuits designed to block such ESD currents from reaching and damaging interior transistors. A wide variety of ESD-protection circuits and devices are in use today. Yet the design of such ESD-protection circuits remains as much of an art as a science.
FIG. 1 is a prior-art ESD-protection circuit. Core circuitry on the IC controls pre-driver 14, which drives the gates of p-channel driver transistor 22 and n-channel driver transistor 24. Driver transistors 22, 24 have their drains connected to I/O pad 10, and drive signals off-chip.
I/O pad 10 can sometimes operate as an input rather than an output. An external signal applied to I/O pad 10 can drive internal circuitry in the core by passing through series resistor 20 and input buffer 12. I/O protection circuit 18 includes series resistor 20 and n-channel grounded-gate transistor 23. When an ESD pulse is applied to I/O pad 10, series resistor 20 can dissipate some of the energy and reduce the voltage on the input of input buffer 12. Grounded-gate transistor 23 can turn on to shunt the ESD pulse to ground, either by normal channel conduction for a negative ESD pulse, or by drain-to-source breakdown (punch-through). A thicker field-oxide may be used for the gate oxide of grounded-gate transistor 23 rather than the more damage-prone thin gate oxide.
A second protection circuit is added for further protection. ESD protection circuit 16 is placed between I/O pad 10 and series resistor 20. An R-C network is attached to the gate of n-channel ESD transistor 26. When an ESD pulse occurs, the rapid rise in voltage is coupled from I/O pad 10 to the gate of n-channel ESD transistor 26 by capacitor 30. The rise in voltage turns on n-channel ESD transistor 26, allowing it to shunt current from I/O pad 10 to ground. This can keep the voltage at the drains of driver transistors 22, 24 below their breakdown voltage, protecting them as well as protecting input buffer 12.
Resistor 28 keeps the gate of n-channel ESD transistor 26 at ground during normal operation. However, during normal operation high-speed signals may couple through capacitor 30 to the gate of n-channel ESD transistor 26, possibly even turning it on, or allowing sub-threshold conduction to occur if not fully turned on. This can degrade input signal quality and even cause false signal reception.
Capacitance is also added to the input, due to the capacitance of capacitor 30. Often large device sizes are needed for protection circuits to handle the large ESD currents. The large device sizes can increase die size and IC cost. The additional capacitance can limit higher-frequency operation. Newer, low-voltage processes can have lower threshold voltages, and thus n-channel ESD transistor 26 may more easily turn on as devices are scaled down. Such unwanted turning on of ESD transistors during normal input switching can hinder IC operation.
What is desired is an ESD-protection circuit for high-frequency and low-voltage circuits. A lower-cost, reduced-die-area ESD structure is desirable, one that has minimal additional capacitance and does not accidentally turn on during normal input switching for normal operation of the IC.